Parallel hardware and software block processing pipelines
US9215472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Feb 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/513
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A block processing pipeline that includes a software pipeline and a hardware pipeline that run in parallel. The software pipeline runs at least one block ahead of the hardware pipeline. The stages of the pipeline may each include a hardware pipeline component that performs one or more operations on a current block at the stage. At least one stage of the pipeline may also include a software pipeline component that determines a configuration for the hardware component at the stage of the pipeline for processing a next block while the hardware component is processing the current block. The software pipeline component may determine the configuration according to information related to the next block obtained from an upstream stage of the pipeline. The software pipeline component may also obtain and use information related to a block that was previously processed at the stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.