Patent · US Active

Compact and low loss Y-junction for submicron silicon waveguide

US9217829B2 · kind B2 · utility

7Cited by
4References
8Claims
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Key dates

Filing dateNov 29, 2013
Grant dateDec 22, 2015
Priority date
Expiry dateMar 1, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG02B2006/1215
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.