Memory device and memory system including the same
US9218312B2 · kind B2 · utility
1Cited by
0References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 16, 2011 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Mar 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4086
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an interface unit and a memory unit. The interface unit receives a clock signal, a command signal and a data signal, internally adjusts input impedance based upon at least one of the command signal and the clock signal, and generates internal control signal of the memory device based upon the command signal and data signal. The memory unit performs read/write operations based upon the internal control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.