Patent · US Active

Reduced bitcount polygon rasterization

US9218679B2 · kind B2 · utility

0Cited by

3References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Jacob Subag · Kiryat Motzkin, IL
Nir Benty · Nahariah, IL

Key dates

Filing date	Oct 8, 2012
Grant date	Dec 22, 2015
Priority date	—
Expiry date	Mar 4, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06T2210/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Techniques are disclosed for carrying out rasterization of a given graphics workload, wherein portions of the workload associated with relatively high bit count operations are processed via a first process path, and portions of the workload associated with relatively lower bit count operations are processed via a second, relatively faster process path, in accordance with an embodiment. In a more general sense, maximal bit count associated with a given primitive can be identified and compared to a threshold to determine which one of multiple available processing paths can be used.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.