Method of memory with regulated ground nodes
US9218857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Oct 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reading data from an accessed memory cell of an accessed column of an accessed section of a memory array includes, in the accessed section, electrically coupling a first voltage source of at least three voltage sources to a corresponding column internal ground node of the accessed column; and electrically coupling the first voltage source to a corresponding column internal ground node of an un-accessed column. The memory array has at least one segment, the at least one segment has at least one section, and each section has at least one column. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.