Memory testing in a data processing system
US9218893B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2013 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Dec 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of memory testing in a data processing system, in response to receiving a request for a hardware memory test during boot process of the data processing system, a controller accesses a stored past memory test result. The past memory test result includes at least a first number of test loops used in a past memory test, an identification of a first test pattern, and an error that occurred in the past memory test. The controller adjusts a second number of test loops and a second test pattern to be used in the hardware memory test according to the past memory test result. The controller then performs the hardware memory test according to the adjusted second number of test loops and the second test pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.