Stacked device and method of manufacturing the same
US9219047B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Jan 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.