Configuration bit architecture for programmable integrated circuit device
US9219067B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | May 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1437
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.