Patent · US Active

Integrated circuit floorplans

US9219483B1 · kind B1 · utility

0Cited by

3References

19Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Christopher F. Lane · San Jose, US
Giles V. Powell · Alameda, US
Jeffrey Tyhach · Sunnyvale, US

Key dates

Filing date	Mar 5, 2014
Grant date	Dec 22, 2015
Priority date	—
Expiry date	Mar 5, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/177
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An integrated circuit is disclosed. The integrated circuit may include an interface circuit region and logic circuitry region. The interface circuit region includes interface circuits that transfers signals in and out of the integrated circuit. The logic circuitry region includes logic circuitry that is configured to implement a logic function. The logic circuitry region surrounds the interface circuit region from at least two sides, from at least three sides, or from all four sides.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.