Integrated driver and related method
US9223153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30132
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit may include a first node, and a first circuit to generate on the first node an inverted replica of an input signal during driver switching between a first supply voltage and a first reference voltage, the inverted replica having a threshold voltage value based upon a second reference voltage greater than the first supply voltage. The driver circuit may include a cascode stage to be controlled by the second reference voltage and to be coupled between a second supply voltage and the first node, a delay circuit to generate a delayed replica of the input signal, an amplifier, and a switching network to couple the control terminal of the active load transistor to one of the first reference voltage and the first node based upon the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.