Patent · US Active

Resolving memory faults with reduced processing impact

US9223663B2 · kind B2 · utility

2Cited by
9References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 22, 2012
Grant dateDec 29, 2015
Priority date
Expiry dateDec 23, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F12/06
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A fault occurs in a virtual environment that includes a base space, a first subspace, and a second subspace, each with a virtual address associated with content in auxiliary storage memory. The fault is resolved by copying the content from auxiliary storage to central storage memory and updating one or more base space dynamic address translation (DAT) tables, and not updating DAT tables of the first and second subspace. A subsequent fault at the first subspace virtual address is resolved by copying the base space DAT table information to the first subspace DAT tables and not updating the second subspace DAT tables. A fault occurring with association to the virtual address of the first subspace is resolved for the base space and the base space DAT table information is copied to the first subspace DAT tables, and the second subspace DAT tables are not updated.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.