Mobile memory cache read optimization
US9223707B2 · kind B2 · utility
1Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2013 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of enabling cache read optimization for mobile memory devices are described. One or more access commands may be received, from a host, at a memory device. The one or more access commands may instruct the memory device to access at least two data blocks. The memory device may generate pre-fetch information for the at least two data blocks based at least in part on an order of accessing the at least two data blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.