Instruction boundary prediction for variable length instruction set

US9223714B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mauricio Breternitz · Austin, US
• Youfeng Wu · Palo Alto, US
• Peter G. Sassone · Austin, US
• James Mason · Mona Vale, AU
• Aashish Phansalkar · Austin, US
• Balaji Vijayan · Austin, US

Key dates

• Filing date: Mar 15, 2013
• Grant date: Dec 29, 2015
• Expiry date: Dec 4, 2033

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3842
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system, processor, and method to predict with high accuracy and retain instruction boundaries for previously executed instructions in order to decode variable length instructions is disclosed. In at least one embodiment, a disclosed processor includes an instruction fetch unit, an instruction cache, a boundary byte predictor, and an instruction decoder. In some embodiments, the instruction fetch unit provides an instruction address and the instruction cache produces an instruction tag and instruction cache content corresponding to the instruction address. The instruction decoder, in some embodiments, includes boundary byte logic to determine an instruction boundary in the instruction cache content.