Patent · US Active

Memory latency tolerance in block processing pipelines

US9224186B2 · kind B2 · utility

12Cited by
5References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 27, 2013
Grant dateDec 29, 2015
Priority date
Expiry dateJun 21, 2034

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04N19/593
  • WIPO fieldAudio-visual technology
  • WIPO sectorElectrical engineering

Abstract

Memory latency tolerance methods and apparatus for maintaining an overall level of performance in block processing pipelines that prefetch reference data into a search window. In a general memory latency tolerance method, search window processing in the pipeline may be monitored. If status of search window processing changes in a way that affects pipeline throughput, then pipeline processing may be modified. The modification may be performed according to no stall methods, stall recovery methods, and/or stall prevention methods. In no stall methods, a block may be processed using the data present in the search window without waiting for the missing reference data. In stall recovery methods, the pipeline is allowed to stall, and processing is modified for subsequent blocks to speed up the pipeline and catch up in throughput. In stall prevention methods, processing is adjusted in advance of the pipeline encountering a stall condition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.