Compact volatile/non-volatile memory cell
US9224463B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 19, 2012 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Apr 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes at least one memory cell having a first transistor coupled between a first storage node and a first supply voltage; a second transistor coupled between a second storage node and the first supply voltage and a single resistance switching element. Control terminals of the first and second transistors are coupled to the second and first storage nodes respectively. The single resistive switching element is coupled in series with the first transistor and is programmable to have one of first and second resistances. The first storage node is coupled to a first access line via a third transistor connected to said first storage node, and the second storage node is coupled to a second access line via a fourth transistor connected to the second storage node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.