Semiconductor memory device and memory system
US9224469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Jun 16, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to an embodiment includes a memory cell array and a control circuit. The memory cell array includes first lines and second lines intersecting each other, a third line commonly connecting to the first lines, memory cells disposed at intersections of the first lines and the second lines, respectively. The control circuit is configured to execute a state determining operation detecting a voltage of the third line, and adjust a voltage applied to the first lines and the second lines during a resetting operation or a setting operation based on a result of the state determining operation. The resetting operation raises a resistance value of the variable resistance element. The setting operation lowers the resistance value of the variable resistance element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.