Memory test with in-line error correction code logic
US9224503B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 21, 2012 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Feb 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.