Fabricating method of array structure
US9224765B2 · kind B2 · utility
1Cited by
2References
10Claims
0Family size
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Key dates
| Filing date | Sep 23, 2014 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Sep 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.