Array substrate, manufacturing method for the same and display device
US9229286B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 17, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Aug 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
According to one aspect of the present invention, the provided is an array substrate. Specifically, the first conductive strip that is coupled to the first data shorting bar and the second conductive strip that is coupled to the second data shorting bar are formed on the array substrate. The width of the first conductive strip is greater than the width of the first data shorting bar. The width of the second conductive strip is greater than the width of the second data shorting bar. The first conductive strip is overlapped with the second conductive strip. Such a structure of the array substrate effectively increases the overlapped capacitance between the data metal layer and the gate metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.