Capless on chip voltage regulator using adaptive bulk bias
US9229462B2 · kind B2 · utility
4Cited by
3References
21Claims
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Key dates
| Filing date | Jun 30, 2015 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Jun 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/56
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An FDSOI integrated circuit die supplies on an output node a regulated output voltage based on a reference voltage. A pass transistor that passes a first current to the output node. A feedback loop regulates the output voltage by generating a second current based on the first current and applying a control signal to the pass transistor based on the second current. A loop current adaptor adapts a ratio of the first and second currents by adjusting a back gate bias voltage applied to a back gate of loop transistor of the feedback loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.