Multi-chip initialization using a parallel firmware boot process

US9229730B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Eberhard Amann · Rottenburg am Neckar, DE
• Frank Haverkamp · Wangen im Allgäu, DE
• Thomas Huth · Eppelheim, DE
• Jan Kunigk · Eppelheim, DE

Key dates

• Filing date: Dec 17, 2014
• Grant date: Jan 5, 2016
• Expiry date: Dec 17, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/44505
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.