Patent · US Active

Semiconductor chip with adaptive BIST cache testing during runtime

US9229872B2 · kind B2 · utility

0Cited by

3References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Christopher B. Wilkerson · Portland, US
Jawad Nasrullah · Stanford, US
Kelvin Kwan · Santa Clara, US

Key dates

Filing date	Mar 15, 2013
Grant date	Jan 5, 2016
Priority date	—
Expiry date	Jan 10, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.