Method and apparatus for optimal cache sizing and configuration for large memory systems
US9229877B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jul 30, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Oct 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.