System and method for identifying electrical properties of integrate circuits
US9230050B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Sep 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to a raster scan image of the extracted and annotated electrical property values superimposed at their corresponding physical locations onto a physical layout image of the integrated circuit, preferably color-coded to further spotlight potential defects. The visual images are compared to as specified layout design parameters and to as manufactured parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.