Separate microchannel voltage domains in stacked memory architecture

US9230614B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Andre Schaefer · Hersbruck, DE
• Ruchir Saraswat · Swindon, GB

Key dates

• Filing date: Dec 23, 2011
• Grant date: Jan 5, 2016
• Expiry date: Dec 23, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/15311
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels.