Highly linear buffer
US9231579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Nov 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0063
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.