Multi-phase clock generator

US9231604B2 · kind B2 · utility

Assignee

• Shanghai Huahong Grace Semiconductor Manufacturing Corporation · CN

Inventor

• Danfeng Chen · Ningbo City, CN

Key dates

• Filing date: Dec 24, 2014
• Grant date: Jan 5, 2016
• Expiry date: Dec 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K3/0315
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Embodiments provide a multi-phase clock generator. The clock generator includes a loop oscillator, a RC filter, a bias current source and a frequency injection source. The loop oscillator includes N levels of CMOS phase inverters which are connected in series and form a loop, N represents an odd number greater than 1. The N levels of CMOS phase inverters have the same structures, each of which includes a CMOS phase inverter main body and a tail current source which is a current mirror of the bias current source. As an effect of RC filter, a clock input signal inputted by the frequency injection source is applied to the first level tail current source, while other tail current sources are not influenced. Injection locking is induced, such that phase noise and frequency stray can be reduced.