Cancellation of feedback digital-to-analog converter errors in multi-stage delta-sigma analog-to-digital converters
US9231614B2 · kind B2 · utility
3Cited by
8References
23Claims
0Family size
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Key dates
| Filing date | Jun 6, 2014 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Jun 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/416
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a mechanism to digitally correct for the static mismatch of the digital-to-analog converter (DAC) in at least the first-stage of a multi-stage noise shaping (MASH) analog-to-digital converter (ADC). The correction is applicable to continuous-time implementations, and is especially attractive for high-speed applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.