High-performance routers with multi-stage, multi-layer switching and single-stage shared buffering
US9231887B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2013 |
| Grant date | Jan 5, 2016 |
| Priority date | — |
| Expiry date | Jan 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/60
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The subject specification comprises techniques employing multi-stage multi-layer switches for packet switching using fully shared buffers with a scalable switch fabric. A switch component includes a set of input modules (IMs) of switches that receive packets and are associated with a set of central modules (CMs) of switches that are associated with a set of memories. The switch component includes a second set of CMs associated with the set of memories, the second set of CMs being associated with a set of output modules (OMs) that can provide packets as output. A switch management component controls switching of the packets between the IMs and first set of CMs to the memories during a first switching phase, and switching of the packets from the memories to the second set of CMs to the OMs for output during a second switching phase, based on a defined scheduling algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.