Memory devices with selective error correction code
US9235466B2 · kind B2 · utility
13Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Sep 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correction apparatus includes an error correction circuit configured to selectively perform error correction on a portion of data that is at least one of written to and read from a plurality of memory cells of a memory device. The portion of data is at least one of written to and read from a subset of the plurality of memory cells, and the subset includes only fail cells among the plurality of memory cells. The error correction apparatus further includes a fail address storage circuit configured to store address information for the fail cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.