Scalable processing for associating geometries with map tiles
US9235906B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2012 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Jun 3, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/29
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided that utilizes a parallel processing system to determine whether different geometries intersect each tile in a map hierarchy. The method receives a description of a geometry and an identification of a tile in a tile tree. The method utilizes an available processing unit to determine whether the geometry intersects the tile. When the geometry intersects the tile and the tile has child tiles, the method stores several task descriptions that can be assigned to any processing units in the parallel processing system. Each task description includes the description of the portion of the geometry that overlaps the tile and an identification of one of the child tiles of the tile. The method then assigns each of the tasks to an available processing unit to continue down the tree hierarchy to determine whether each child tile intersects a portion of the geometry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.