Semiconductor memory device and data reading method
US9236097B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2012 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Mar 3, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes two memory cell arrays, a sense amplifier shared by the two memory cell arrays; and a control circuit configured to control data readout from the two memory cell arrays. Each memory cell array includes word lines, two or more bit lines, a dummy word line, memory cells provided at intersections of the bit lines and the word lines, and dummy cells provided at intersections of selected bit lines and the dummy word line. When the control circuit reads data from one memory cell array, the control circuit activates the dummy word line included in the other memory cell array and generates, with the dummy cell included in the other memory cell array, a reference level of the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.