Circuit for enhancing robustness of sub-threshold SRAM memory cell

US9236115B2 · kind B2 · utility

Assignee

• SOUTHEAST UNIVERSITY · CN

Inventors

• Na Bai · 安丰镇, CN
• Longxing Shi · Nanjing, CN
• Jun Yang · 埔鹽鄉, TW
• Xinning Liu · Nanjing, CN
• Jiafeng Zhu · San Ramon, US
• Yue Feng · Beijing, CN
• Cai Gong · 安丰镇, CN
• Fei Pan · 安丰镇, CN
• Hong-Shi Chang · 安丰镇, CN
• Yifeng Deng · Longbeilingcun, CN
• Yuan-Ning Chen · Taipei, TW
• Yingcheng Xia · 安丰镇, CN

Key dates

• Filing date: Dec 27, 2012
• Grant date: Jan 12, 2016
• Expiry date: Dec 27, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.