Shared-gate vertical-TFT for vertical bit line array
US9236122B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Jul 24, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.