Systems and methods for mitigation of mechanical degradation in high performance electrical circuit packages
US9236336B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2013 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Aug 2, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers. Further, the package substrate includes a plurality of metallic elements disposed within the plurality of voids and electrically isolated from the generally uniform metallic layer, the metallic elements configured to reduce a physical size of respective voids without electrically contacting the generally uniform metallic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.