Analog circuits having improved insulated gate transistors, and methods therefor
US9236466B1 · kind B1 · utility
3Cited by
420References
23Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 5, 2012 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Feb 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.