Fractional divider based phase locked loops with digital noise cancellation
US9236873B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Dec 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is provided to generate a PD output signal in response to the FD output signal and REF_CLK. A loop filter is provided to generate the digital control input signal in response to the PD output signal as modified by a noise cancellation signal (NCS). The NCS is generated to at least partially compensate for non-random deterministic noise in the MMD output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.