Interprocessor communications systems and methods
US9236884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2013 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Jan 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0072
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.