Cavity package design
US9238579B2 · kind B2 · utility
3Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Mar 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device. The device including a substrate having electrical traces, at least one of a MEMS die and a semiconductor chip mounted on the substrate, and a spacer. The spacer has a first end connected to the substrate and includes electrical interconnects coupled to the electrical traces. The at least one MEMS die and a semiconductor chip are contained within the spacer. The spacer and substrate form a cavity which contains the at least one MEMS die and a semiconductor chip. The cavity forms an acoustic volume when the semiconductor device is mounted to a circuit board via a second end of the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.