Capacitive sensor integrated onto semiconductor circuit
US9239310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Jan 10, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N27/228
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an ASIC, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the ASIC; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.