Method, apparatus, and system for energy efficiency and energy conservation including balancing power among multi-frequency domains of a processor based on efficiency rating scheme
US9239611B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2011 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Dec 12, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.