Integrated circuit having voltage mismatch reduction
US9240233B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Nov 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a first circuit portion comprising a plurality of first cells, each first cell comprising a first transistor having a first voltage value at a first node, and a second transistor having a second voltage value at a second node. A second circuit portion comprises a plurality of second cells. The second cells are individually coupled with a corresponding first cell of the plurality of first cells. The second cells are selectively controllable to supply a voltage to one or more of the first cells based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.