Method for manufacturing array substrate by forming common electrode connecting NMOS in display area and PMOS in drive area
US9240353B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 9, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Dec 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an array substrate includes: forming a shielding layer, an insulating buffer layer, active layers, a gate insulating layer and NMOS gate electrodes in a display area and a drive area on a substrate in sequence; forming a PMOS gate electrode in the drive area on the foregoing substrate, in which the NMOS gate electrodes and the PMOS gate electrode are provided on the same layer; meanwhile forming a first through hole in a common electrode connecting area, in which the first through hole is configured to connect the shielding layer and a source/drain electrode layer; forming an intermediate insulating layer on the foregoing substrate, forming a second through hole in the common electrode connecting area and third through holes in the display area and the drive area, in which the second through hole is formed at a same position as the first through hole and configured to connect the shielding layer and a source/drain electrode layer, and the third through holes are configured to connect the active layers and the source/drain electrode layer; and forming the source/drain electrode layer on the foregoing substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.