Method for fabricating embedded chips
US9240392B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Jun 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0362
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating embedded die packages including the following steps: obtaining a honeycomb array of chip sockets such that each chip socket is surrounded by a framework having a polymer matrix of a first polymer and at least one via post through the framework around each socket; placing the honeycomb array on a transparent tape so that an underside of the honey comb array contacts the transparent tape; positioning a chip terminal the down (flip chip) in each chip socket so that undersides of the dies contact the transparent tape; using optical imaging through the tape to align the chips with the via posts; applying a packing material over and around the chips in the honeycomb array, and curing the filler to embed the chips on five sides; thinning and planarizing the packing material to expose upper ends of the vias on upper side of the array; removing the transparent tape; applying a feature layer of conductors on the underside of the honeycomb array and the undersides of the chips, to couple at least one terminal of each die to at least one through via; applying a feature layer of conductors on over side of the honeycomb array such that at least one conductor extends from …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.