Passive-matrix display and tiling display
US9240438B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Apr 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A passive-matrix display of the disclosure includes a first electrode disposed over a substrate, a second electrode disposed over the first electrode and three-dimensionally intersecting the first electrode, a first auxiliary electrode disposed between the substrate and the first electrode, three-dimensionally intersecting the first electrode and being parallel to the second electrode, and a second auxiliary electrode parallel to the first auxiliary electrode and to the second electrode, the first electrode and the first auxiliary electrode being electrically connected by a first connection portion, and the second electrode and the second auxiliary electrode being connected by a plurality of second connection portions each disposed with at least one of the first electrodes therebetween. The passive-matrix display enables voltage drop and variation in brightness to be reduced by lowering the wiring resistance of the second electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.