Manufacturing method of power MOSFET using a hard mask as a CMP stop layer between sequential CMP steps
US9240464B2 · kind B2 · utility
8Cited by
1References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 14, 2014 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | May 29, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.