Enhanced GaN transistor and the forming method thereof
US9240474B2 · kind B2 · utility
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Key dates
| Filing date | Oct 10, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Oct 10, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
Abstract
An enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.