Homogeneous dual-rail logic for DPA attack resistive secure circuit design
US9240786B2 · kind B2 · utility
2Cited by
3References
21Claims
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Assignee
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Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HURL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HURL circuit has a differential power at a level that is resistive to DPA attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.