Method for producing a structure for microelectronic device assembly
US9241403B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Jan 19, 2016 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Forming of a microelectronic device including a substrate containing at least one conductive pad, the pad being provided with a bottom surface resting on the substrate and an upper surface opposite the bottom surface. The upper surface of the pad has a stack applied thereto formed of a conductive layer and a protective dielectric layer including an opening called first opening facing the pad and exposing the conductive layer. At least one insulating block is arranged on a peripheral region of the upper surface of the pad, the insulating block having a cross-section forming a closed contour and having an opening called second opening. A conductive pillar is located in the center of the contour in the second opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.