Fractional-N spread spectrum state machine
US9244484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2013 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention may be realized in a fractional-N spread spectrum clock (SSC) generator utilizing an SSC state machine generating a single clock gating signal to drive a fractional-N phase locked loop (PLL) frequency multiplier to generate an SSC output clock. The SSC generator leverages upon the development of the digital PLL to implement the SSC generator within the final core PLL. The SSC generator only requires a relatively low base frequency reference clock and digital programming including an SSC rate and a modulation definition signal to produce the fractional-N spread spectrum output clock. The SSC generator results in cost savings through a high frequency SSC output clock generator that utilizes a relatively slow reference clock without the need for multiple high frequency clocks or multiple feedback clocks to drive the PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.